Chapter 11: added Input and Output columns to the standard and
extended KERNAL jump tables and to the Hypervisor services table, from
the MEGA65 Book.
Chapter 11: corrected the standard KERNAL entries that differ from
the C64. KEY, MONEXIT, ScanStopKey and SCRORG replace SCNKEY, SETTMO,
UDTIM and SCREEN; MEMTOP, MEMBOT and IOBASE are reserved.
Chapter 11: documented PLOT's registers as on the C64, with the line
in X and the column in Y, measured from the current window's
origin.
Chapter 11: added the MEGA65's own KERNAL entries, VERSIONQ to
ADDKEY at $FF2F-$FF4A, to the extended
table.
Chapter 11: described VERSIONQ under "Identifying the version",
including the ROM release that added it (920417), and the version string
at $20016, which is discouraged.
Chapter 11: noted the ROM release that added each MEGA65 entry in
the extended KERNAL table.
Chapter 15: replaced the advice to check SETBNK's argument order
with the order itself.
Fixed the em dash in every chapter's page title.
Chapter 5: corrected $D030 bits 1, 2 and 6 (EXTSYNC,
PAL and the unimplemented CROM9), the MULBUSY status bit, which is never
set, and the description of the ROM in bank 2.
Chapter 8: corrected which $D030 bits need the VIC-III
personality, the cycle cost of flat [zp],Z access, and the
location of EXTIRQS and FNRSTCMP in $D07A; noted that DMA
options carry over between chained jobs.
Chapter 11: replaced the ROM layout with the layout of ROM 920422;
corrected the serial-bus and editor vectors ($0334-$034B,
two bytes apart), VECTOR's 56-byte table from ROM 920400, and the
registers the KERNAL saves before jumping through CINV.
Chapter 8: noted when the $00 speed shortcut has no
effect.
Chapter 16: added machine-language examples for paddles, using the
MEGA65's $D620-$D623, and for the keyboard matrix; gave the
light pen registers and noted that the current core latches only touch
input.
Appendices: $D640-$D67F as the Hypervisor trap range,
$D05E as the low byte of CHRCOUNT, and the RTN/RTS #$nn
naming.
Chapter 1: stated the ROM and core the book was checked against, and
listed the features that need a ROM newer than the stable release.
Added an "Updated" date to each chapter changed since first
publication.
Chapter 1: colour RAM is 32KB; the internal card slot takes a
full-size SD card; sourced the project's founding and the C65's two
SIDs.
Chapter 5: corrected attic RAM (only Nexys boards lack it), the
colour RAM window, CRAM2K, $D030 in the C64 personality,
and which personalities have the Hypervisor traps; removed an
unsupported claim about the name chip RAM.
Chapter 8: Matrix Mode runs on its own helper processor; Hypervisor
file names are case-insensitive but must be ASCII; corrected the IEC
slowdown, BRK breakpoints, the RESTORE timing, Xemu's watchpoints and
trap $70; the takeover procedure now uses
rom_writeenable ($D641) rather than the
$70 toggle.
Chapter 11: explained that the far-call routines run from a RAM copy at
$0380, and why programs must call them through the jump
table: their RAM addresses moved between ROMs 920413 and 920414.
Chapter 12: a row ended by $FFFF ignores LINESTEP, which
makes it easy to build a screen one line at a time.
Chapter 12: GOTOX Y offset, negative Y offset, ROWMASK and sprite
priority bits; character flip bits; BOLDISALT (development cores).
Chapter 13: per-SID panning with SIDEXENA. Chapter 8: Matrix Mode
single-stepping (t1, t2, t0) and watchpoints. Chapter 17: 15 kHz CRT
output (development cores).
Checked the 50 most recently merged mega65-core pull requests against
the book. Chapter 7 and 10: RTN #n needs core 0.97 or later. Chapter 8:
DMA addresses wrap within a megabyte unless option $01 or
$D703 bit 1 is set; on 0.97, line mode draws two pixels
short; an INQ/DEQ problem when single-stepping on 0.97. Chapter 13: the
OPL2 synthesiser exists, and NTSC CIA timing differs on 0.97. Chapter 16:
$D619 reads $FF when the queue is empty.
Chapter 17: the Audio amplifier setting does not affect the 3.5mm jack
on current cores.
Chapter 11: filled in the $D640 table's mkfile row from
the Hypervisor source: partly implemented, with its inputs, errors and
limits.
Chapter 11: $FF80 is always $FF; PR #946
is not yet merged; corrected the summary, the error-code note and the
trap personalities.
Chapter 16: JOYSWAP does not swap paddles or extra buttons; RMOUSE
cannot detect a missing mouse; the mouse driver runs in the KERNAL's
interrupt; fixed the mouse example.
Chapter 2: LOAD and SAVE also default to drive 8; TI counts
microseconds, not frames; Freezer details and citations corrected.
Chapter 3: corrected CHANGE, INPUT, SCNCLR, IF...ELSE, BANK, FRE(4)
and FRE(5) (from ROM 920415), MKDIR and CHDIR, MOUNT with no file name,
the COLOR range, DMODE, CHAR, LPEN and RMOUSE; fixed the WAIT, TRON, FIND
and file-writing examples.
Chapter 4: FIND with quotes misses keywords; CHANGE asks before
replacing; RENUMBER can break FGOTO and FGOSUB; corrected two
troubleshooting entries.
Chapter 6: integers are stored high byte first; EDMA reverses both
addresses with 48, not 32; dated SYS TO (920414), its I mode (920419)
and FRE(4)/FRE(5) (920415); fixed the token dump, the sort helper's
pointer arithmetic, and the TRAP example's explanation.
Chapter 9: AND cannot split an array address, so the examples use
MOD; plain SYS keeps registers you leave out; LOAD always uses
$2001; only banks 4 and 5 are free for code; corrected the
BASIC header listing and the SYS TO I range.
Chapter 17: how the clock works on R4 and later boards: one queued
write at a time, reads from a copy, which addresses are safe to write,
and that hundredths of a second always read 0 on current cores, with a
BASIC example that writes the battery-backed RAM safely.
Chapter 14: DSAVE cannot save to unit 12, while LOAD and TYPE can;
d81attach0/1 are deprecated in favour of attach; corrected what the SD
card utility copies; removed an unsupported claim about loadfile_attic.
Chapter 11 also marks d81attach0/1 as deprecated.
Chapter 15: BOOT runs AUTOBOOT.C65 as BASIC, so machine code needs a
stub or BOOT "name"; FORMAT asks for confirmation; @ replaces data files
too; MKDIR and CHDIR work only on the MEGA65's own drives; error range
20-29 includes write errors; and the IEC compatibility claim is
narrowed.
Chapter 17: the RTC example now masks bit 7 of the hours; R4 and
later boards have 16 bytes of battery-backed RAM, not 64; the UART is
not connected on current boards and has no interrupts yet; NTSC has 263
VIC-II lines; corrected the cartridge and battery descriptions.
Chapter 10: PHW pushes the low byte first, so a PHW word is not a
ready-made pointer; BIT immediate also sets N and V (a fifth difference
from the 65C02); PLP and RTI never change E; BRK sets B only in the
pushed copy of P; only LDQ adds Z in indirect quad modes; noted the
6502 compatibility mode, cc65's LBSR, and removed the unsupported ADDQ
spelling.
Chapter 7: the stack-parameter example used PHW, which leaves the
pointer the wrong way round; it now pushes the bytes with PHA. Removed
the unsupported ADDQ and LDR Q spellings.
Chapter 5: programs should still test MULBUSY before reading
MULTOUT, although current cores never set it.
Chapter 12: corrected the palette banks (text and bitplanes share
one), NCM (a property of any SEAM character; nybble 0 is the
background), the effect of attributes on FCM, 16-colour sprite palette
entries, and what BASIC's SPRITE supports; removed an unsupported claim
about SCREEN's arguments and a citation that did not cover the sprite
pointer list.
Chapter 13: fixed the SOUND example, which silenced itself; SOUND's
sweep is a step, not a range; portamento does not stop notes ending in
current ROMs; the mixer example now waits after selecting a register;
NOMIX affects only the PWM outputs; gave SIDMODE's bit order and the SID
read-back copy; noted audio DMA interrupts in development cores; and
corrected three citations.
Chapters 5 and 12: colour RAM is 32KB on every model, not 64KB on
some; a COLPTR offset of $8000 or more wraps round.
Chapter 11: corrected the description of ROM version numbers.
92xxxx and 99xxxx are not successive series: 92xxxx are release and beta
ROMs, and 99xxxx are development ROMs built in parallel.
Chapter 10: STQ sets N and Z from A, because the CPU runs its
$42 $42 prefix as two NEG instructions.
Chapter 12: a SEAM screen word of $FFFF ends the row;
LINESTEP must be at least, not exactly, twice CHRCOUNT.
Contents page: listed Appendices A–G, each linking to its section.
Added the version and this changelog to the contents page.
First publication of Chapters 1–17 and the appendices.