Programming the MEGA65 — Chapter 10: Vocabulary of the 45GS02

Oct 4, 2026 · Updated Oct 11, 2026 · @Craig Taylor

Introduction

This chapter is a reference to every instruction the 45GS02 executes, in alphabetical order. Each entry gives the operation, the flags it changes, every addressing mode with its opcode, and which processor introduced it. The opcodes follow the cc65 project's CPU reference (ca65/da65 CPU overview), which documents the 6502, 65C02, 65CE02, 4510 and 45GS02 instruction sets side by side.

The 65CE02 defines all 256 opcodes, and the 45GS02 builds its extensions from prefixes rather than new opcodes, so every byte value is a valid instruction or prefix. In its native mode there are no undocumented opcodes of the kind C64 programmers know; a separate 6502 compatibility mode, which the Book describes as incomplete and untested, emulates some of them (MEGA65 Book, 45GS02 and 6502 instruction sets appendix).

Cycle counts are not given here. The 45GS02's native timings differ from the 6502's, and at 40.5 MHz they also depend on memory type and wait states; Chapter 7 discusses timing, and the MEGA65 Book's CPU chapter is the authority.

Addressing mode abbreviations

In the opcode columns, two-byte sequences such as $EA $72 are prefixed instructions: the prefix byte comes first, then the opcode and its operand.

Flags

The flags column lists the flags an instruction can change, using N, V, E, B, D, I, Z and C as in Chapter 7. A dash means no flags are affected. The flags column refers to the Z flag, never the Z register.

Origin

Assemblers do not all use the same mnemonics for the newer instructions. Long branches may be written LBNE or chosen automatically from BNE; quad instructions may be written ADCQ (cc65 and the MEGA65 Book) or ADQ (64tass); and bit instructions may be written RMB3 $10 or RMB 3,$10. This chapter uses the forms most common in MEGA65 documentation.

ADC to BVS

Notes

ADC and SBC honour the D flag, working in binary-coded decimal when it is set. Clear D with CLD at the start of any program that does not set it deliberately.

BBR and BBS take two operands: the base page address to test and an 8-bit relative branch target, as in BBS3 $10,done. They are three-byte instructions.

BIT immediate sets Z from A AND the operand, and, unlike the 65C02, also copies bits 7 and 6 of the operand into N and V, just as the memory modes do (MEGA65 Book, BIT instruction entry; mega65-core, gs4510.vhdl, September 2026).

BSR is written LBSR in cc65 (cc65 CPU reference); the MEGA65 Book writes BSR.

BRK sets I. The CPU has no stored B flag: bit 4 is set only in the copy of P that BRK pushes, so a handler tells BRK from IRQ by testing that copy on the stack (mega65-core, gs4510.vhdl, September 2026).

BRK is followed by a padding byte that the CPU skips on return, as on the 6502. The return address pushed is that of BRK plus two.

BSR pushes the return address like JSR, so a subroutine called with BSR returns with RTS or RTN. Because the target is relative, code built with BSR can run at any address without relocation.

CLC to EOR

Notes

CLE should be used only where the program's stack can safely grow beyond page 1. The KERNAL and BASIC expect the 8-bit stack, so cooperative routines should leave E set.

Compare instructions set C when the register is greater than or equal to the operand, treating both as unsigned, and set Z when they are equal. N reflects bit 7 of the difference.

DEW works on a 16-bit value at a base page address, low byte first. Its flags reflect the 16-bit result.

EOM is the 6502's NOP, $EA. After MAP it ends the interrupt-blocked mapping sequence. Placed before an instruction that uses (bp),Z, it acts as the flat-addressing prefix described in the last section of this chapter, so a stray NOP before such an instruction changes its meaning.

INC to PLZ

Notes

PLP and RTI restore N, V, D, I, Z and C from the stack, but never E: only CLE and SEE change the stack mode (MEGA65 Book, PLP and RTI instruction entries; mega65-core, gs4510.vhdl, September 2026).

INW increments a 16-bit value at a base page address, low byte first. It is the 45GS02's most common way to advance a pointer.

JMP (abs) with a vector at an address ending in $FF behaves differently on the NMOS 6502, which fetches the high byte from the start of the same page. Avoid placing vectors at $xxFF, and code will behave the same on every member of the family.

JSR (abs,X) calls through a table of 16-bit addresses. With X holding twice a command number, it dispatches commands in one instruction.

LDZ has no base page modes. To load Z from base page, use LDA and TAZ.

MAP reads its arguments from all four registers; see Chapters 5 and 8. It also gives the megabyte selector when X or Z holds $0F.

PHW pushes the low byte first, so the high byte ends up at the lower stack address. That is the reverse of how JSR leaves a return address, and it means a word pushed with PHW is not a ready-made little-endian pointer for stack-relative addressing (mega65-core, gs4510.vhdl, September 2026; Xemu, cpu65.c). PHW abs pushes the 16-bit contents of the address, not the address itself.

RMB to STZ

Notes

RMB and SMB are two-byte instructions that change one bit without affecting the others or the flags. They are ideal for flag bytes shared between a main program and an interrupt handler, since each is a single uninterruptible instruction.

RTN #n pops the return address as RTS does, then discards n further bytes, cleaning up parameters the caller pushed before the call. It works only on core 0.97 and later; on earlier cores it fails, usually crashing the program (mega65-core PR #791).

SBC needs C set before a subtraction without borrow, as on the 6502.

STX abs,Y and STY abs,X fill gaps in the 6502's instruction set, which had only base page forms of indexed STX and STY.

STZ uses the same opcodes as the 65C02's "store zero" but stores the Z register. While Z is zero the result is identical; once a program uses Z for anything else, 65C02 code that relies on STZ to clear memory breaks. See Chapter 7.

TAB to TZA

Notes

TAB takes effect immediately: the very next base page instruction uses the new page. Set B back to zero before calling the KERNAL or returning to BASIC.

TRB and TSB set or clear, in memory, the bits that are set in A, and set the Z flag from the bits that were already common to both. They are the natural way to change single bits of hardware registers, such as LDA #$40 : TSB $D031, and they leave A unchanged.

TSY and TYS reach the high byte of the stack pointer. With E set, the stack is 8 bits wide and wraps within a single 256-byte page, the page given by the high byte; it is page 1 after reset, and TYS can move it elsewhere. With E clear, the stack pointer is a full 16-bit value.

TXS sets only the low byte of SP. With the 16-bit stack enabled, set the high byte with TYS as well.

The Quad Instructions

The quad instructions operate on the 32-bit Q register, formed from A (bits 7-0), X (15-8), Y (23-16) and Z (31-24). Each is an ordinary 8-bit instruction preceded by the prefix $42 $42; the opcodes below give the full sequence. Flat indirect forms add the $EA prefix after it.

The mode list follows the cc65 assembler's 45GS02 table. Other assemblers name some of these differently: 64tass, for example, writes ADQ and LDQ as forms of its own mnemonics, and treats INQ and DEQ as implied-only, using other names for the memory forms. Check your assembler's documentation for the spelling it expects.

Notes

STQ changes flags. Unlike STA, STQ is not flag-neutral. The CPU executes the $42 $42 prefix as two NEG instructions before the store: A ends up unchanged, but N and Z are set from it (MEGA65 Book, STQ instruction entry). Don't rely on flags from an earlier instruction surviving an STQ. The other quad instructions set N and Z from their own results, so the prefix makes no difference to them.

Indirect quad modes are written (bp) and [bp] for every instruction except LDQ, which cc65 writes (bp),Z and [bp],Z. Because Z is part of Q, the other indirect quad instructions do not add Z to the pointer at all; only LDQ does, which is why cc65 writes its modes with ,Z. Set Z to zero before an indirect LDQ (mega65-core, gs4510.vhdl, September 2026).

Flags reflect the whole 32-bit result: N is bit 31, and Z is set only if all 32 bits are zero.

Every quad instruction that changes Q changes A, X, Y and Z. Save any of them that hold values you still need.

Prefixes and Encoding Notes

The 45GS02 adds its extensions without new opcodes. Instead it gives special meaning to sequences of existing one-byte instructions placed in front of an ordinary instruction.

NEG and NOP were chosen because they are single-cycle instructions on the C65's CPU, and the 65CE02 does not take an interrupt immediately after a one-cycle instruction. An interrupt therefore cannot arrive between a prefix and the instruction it modifies (Xemu issue #202).

Consequences for programmers

Disassembly. A disassembler that does not know the 45GS02 shows prefixes as separate NEG and NOP instructions. Reading NEG, NEG, LDA $10 as three instructions gives the wrong meaning: it is a single LDQ $10.

Self-modifying code. Code that patches an instruction must patch the whole prefixed sequence, and branch targets must point at the first prefix byte, not into the middle of the sequence.

Unintended prefixes. A NOP placed for timing or padding immediately before a (bp),Z instruction turns it into a flat access, and a NEG of A immediately followed by another NEG creates a quad prefix. Place padding NOPs elsewhere, and do not negate A twice in a row.

Differences from the 65C02

Code written for the 65C02 mostly runs unchanged, but five differences can catch it out:

With Z held at zero, the first two differences disappear. The third matters to 65C02 code that tests N or V after a BIT immediate. The last two matter only for code written for WDC's 65C02 variant, which the MEGA65 has never needed to run.